1. Technical Field
This invention relates generally to resistive memory devices, and more particularly, to methods for improving performance of resistive memory devices.
2. Background Art
Recently, resistive memory devices have been developed for use in storage applications in electronic devices. A typical resistive memory device is capable of selectively being placed in a low resistance (“programmed”) state and a high resistance (“erased”) state. The state of the device is read by providing an electrical potential across the device and sensing the level of current through the device. These devices are appropriate for use in a wide variety of electronic devices, such as computers, personal digital assistants, portable media players, digital cameras, cell phones, automobile engine controls and the like. While such devices have proven effective in use, it will be understood that it is desirable to improve performance thereof. For example, improvements in erase performance and reduced current leakage are being sought.
FIGS. 1-5 illustrate a metal-insulator-metal (MIM) resistive memory device 20 and operating characteristics thereof. With reference to FIG. 1, the device 20 includes a Ta or TaN bottom electrode 22, a deposited or grown Ta oxide layer 24 on the electrode 22, and a top Al electrode 26 deposited on the Ta oxide layer 24, which deposition, undertaken at a temperature of for example 190° C., causes formation of a thin (for example ˜20 angstroms thick) Al oxide layer 25 between the Ta oxide layer 24 and the electrode 26, so that Ta oxide layer 24 and Al oxide layer 25 make up the insulating layer of the MIM device 20. The electrode 22 is connected to a transistor 28 so that the device 20 is in series with the transistor 28.
The programming of the device 20, i.e., the changing of the device 20 from a high resistance (erased) state to a low resistance (programmed) state is described with relation to FIGS. 2 and 5, the curve A illustrating programming characteristics of the device 20. As shown therein, a positive voltage +V is applied to the electrode 26, while terminal 23 is held at ground, so that higher to lower potential is applied in the direction from electrode 26 to electrode 22. This potential is increased (by increasing +V applied to electrode 26 and holding terminal 23 at ground), resulting in current flow with increasing potential as shown at A1. When this potential reaches ˜5.3V, the device 20 switches into a low resistance state (indicated at A2), and current increases rapidly with increased potential until current is limited to a selected level A3 by current limiting transistor 28 (gate voltage Vg1).
Erasing of the device 20, i.e., the changing of the device from a low resistance (programmed) state to a high resistance (erased) state is described with relation to FIGS. 3 and 5, the curve B illustrating erasing characteristics of the device 20. As shown therein, a positive voltage +V is applied to the terminal 23, while the electrode 26 is held at ground, with Vg2 applied to the gate of the transistor 28 greater than Vg1 of FIG. 2, so that higher to lower potential is applied in the direction from electrode 22 to electrode 26. This potential is increased (by increasing +V applied to terminal 23 and holding electrode 26 at ground), resulting in current flow with increasing potential as shown at B1. When this potential reaches ˜1.2V, the device 20 switches into an erased (high resistance) state (indicated at B2). With further increase in this potential, the device 20 remains in its erased state until the potential reaches ˜1.8V, whereupon the device 20 switches back to its programmed (low resistance) state (indicated at B3).
The memory device 20 may be erased using a second approach (FIGS. 4 and 5). In this approach, the erase electrical potential is applied across the memory device 20 from higher to lower potential in the direction from the electrode 26 to the electrode 22, i.e., in the same direction as applied in the programming of the device 20, by applying +V to the electrode 26 and holding terminal 23 at ground.
The increase in resistance from the conductive state to the erased state (indicated by small decrease in current E1, FIG. 5) is relatively small. This shallow erase causes relatively small ON-OFF ratio, i.e., the ratio of the ON state resistance to the OFF state resistance. Increasing the voltage V+ does not improve the situation as it has been found that further increase in V+does not increase the level of erase resistance and that after a relatively small increase in V+, the device returns to its programmed state (FIG. 5).
Furthermore, the range of potentials R1 which achieve erasure of a programmed device 20 is relatively small, i.e., 0.6V, that is, any of a plurality of applied potentials in the range or window from ˜1.2V to ˜1.8V will achieve erase of a programmed device 20. However, an applied potential outside this range R1 will not provide an erased state of a programmed device 20. Control of the erase potential so that it falls within such a small range R1 can be problematical.